Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavioral descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design of a layout and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product.
SPICE is a common type of simulator that is used to simulate and verify the operation of an electronic design. With SPICE, the electronic design is converted into a system of equation(s), which is then solved for a given set of inputs to check the state of specific portions of the circuit at given points in time. For many circuit designs, this process can be a very computationally expensive and time-consuming effort, especially given the size and complexity of modern circuit designs.
Even after simulation has occurred, further changes may still be introduced to the electronic design. For example, post-simulation layout edits may result in changes to the position and/or composition of components on the design layout. With these layout changes, there is usually also the need to perform another round of simulation on the new version of the design to check and account for the performance effects of those changes.
The problem is that even though the edits may occur in a limited manner to only a small percentage of the components and/or area of the overall layout, conventional approaches to implementing simulators such as SPICE may nonetheless require the entire design to be re-simulated. Because of the integrated nature of the system of equations created in SPICE for the circuit, post-layout edits will require the system of equations to be reformulated, and the entire circuit to then be re-simulated. This process incurs significant costs in terms of computational expense and time delays, even though much of the layout may have been entirely unchanged by the edits.
Therefore, there is a need for an improved approach to perform simulation that addresses these problems with the conventional approaches.